A soft error upset (SEU) refers generally to a change of state or a transient induced in one or more signal values in a semiconductor device (e.g., when struck by an ionizing particle, such as a neutron or an alpha particle). For example, a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a complex PLD (CPLD), are configured by data stored in configuration memory cells (e.g., SRAM cells), which are susceptible to SEUs that change the originally programmed data state (e.g., programmed a “1” but SEU changes value to “0”). One or more SEUs within the PLD may be particularly noticeable because the data stored in the configuration memory cells determines the PLD's functionality.
One conventional approach, for example, to the PLD's SEU vulnerability includes replacing the SRAM-based configuration cells with non-volatile memory cells (e.g., EEPROM zero power memory cells). However, non-volatile memory cells generally require more silicon area and are often more expensive to implement. Another approach employs mask changes to hardwire the SRAM configuration cells to their desired value (e.g., “0” or “1”) based on a given design and application or to convert the design to an application specific integrated circuit. A drawback of this approach is that the hardwired SRAM configuration cells or ASIC can no longer be reprogrammed, which is a fundamental benefit of a PLD. Furthermore, testing often becomes difficult because the test procedures typically rely on the PLD's programmability for full testability by the manufacturer. As a result, there is a need for improved techniques directed, for example, to SEU issues associated with PLDs or other programmable memory devices.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.